Four integrated programmable microengines (MEv2) with 8K instruction program stores running up to 900 MHz | Flexible multi-threaded RISC processors can be programmed to deliver intelligent transmit and receive processing, with robust software development environment for rapid product development |
Integrated Intel XScale® core:
| 32 Kbytes - Instruction cache | | 32 Kbytes - Data cache | | Up to 1,200 MHz |
| Embedded 32-bit RISC core for high performance processing of complex algorithms, route table maintenance and system-level management functions. Lowers system cost by eliminating external host processor. |
Integrated 512 Kbytes L2 push cache performance | Improves CPU performance and MEv2 to Intel XScale core and PCI to Intel XScale core communication |
Two unidirectional 32-bit media interfaces (Rx and Tx) programmable as SPI-3 or UTOPIA
Each path configurable for 4x8-bit, 2x16-bit, 1x32-bit or combinations of 8 & 16-bit data paths | Supports industry standard cell and packet interfaces to media and fabric devices; simplifies design and interface to custom ASIC devices
Supports up to 127 ports using a 16-bit UTOPIA-2 MPHY mode |
Two integrated Gigabit Ethernet MACs | Lowers system cost, power and board real estate |
Two integrated 10/100 Ethernet MACs | Can be used as debugging ports or control signal ports. Lowers system cost, power and board real estate. |
Integrated high speed serial controller: | 256 HDLC channel controller (64 channels when configured with dynamic timeslot remap) | | ATM-TC | | Up to 16xT1/E1/J1 TDM links |
| Performs inverse multiplexing over ATM (IMA), which provides lower system cost, power and board real estate |
Integrated cryptography accelerator | Provides up to 200 Mbps bulk encryption (DES/SHA-1) capability. Supports AES, DES and 3DES encryption algorithms as well as SHA-1 and MD5 hashing algorithms. |
Two industry standard DDR DRAM interfaces: | One 64-bit + ECC DDR300 low latency channel (up to 2GB) optimized for microengine use (not available on 300 MHz ME configuration) | | One 32-bit + ECC DDR300 low latency channel (up to 1GB) optimized for the Intel XScale core |
| Memory subsystem supports the network processor store-and-forward processing model. Separate memory channels for Intel XScale core and microengines improves data plane and control plane performance. |
I/O coherency for Intel XScale core DRAM | Improves performance through accelerated control plane/data plane communications |
One industry standard QDR SRAM interface (not available on 300 MHz ME configuration) | Provides industry standard interface for memory subsystem for look-up tables and access lists, or co-processors (such as CAM/TCAM) |
Asynchronous control interface supports 8 or 16-bit slow port devices via 16-bit expansion bus | Provides control interface for connecting to microprocessor port of PHY devices and flash memory. Provides a direct connection to DSP via HPI. |
Hardware support for memory access queuing | Simplifies application development and reduces system cost |
JTAG support | Improves hardware debug ability |
Intel® IXA Software Development Kit (SDK) Intel® Hardware Development Platform | Industry standard AdvancedTCA* form factor hardware reference design and state of the art development tools improves time to market via robust hardware and software development tools |
1752 ball FCBGA 42.5 mm x 42.5 mm package | Minimizes board layers, providing easier board layer routing and lower cost |
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