Intel XScale® core
| Available at 266 MHz, 400 MHz, 533 MHz and 667 MHz |
| Delivers high MIPS/power consumption ratio and provides ample processing headroom for value-added software features |
32-bit 33/66 MHz PCI v2.2, host and option interface | Provides flexibility to directly connect devices including 802.11x chips, PCMCIA controllers and cable MACs/PHYs |
USB
| USB v. 1.1 device controller | | USB v. 2.0 host controller, supports low-speed and full-speed modes only |
| Industry-standard interface for connection to a wide array of devices |
32-bit, DDR1-266 SDRAM interface
| Optional ECC | | 32MByte to 1GByte of memory |
| | High-bandwidth memory interface | | Optional ECC improves system reliability |
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32-bit Expansion bus interface with parity
| Master/Target capable | | 25-bit address |
| | Glueless connection to most other devices | | External mastering capability allows external devices to communicate with each other and with internal peripherals resulting in shared memory subsystem design and lower system cost> |
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Integrated Ethernet MACs
| Up to three integrated 10/100 Ethernet MACs with SMII interface | | Up to three integrated 10/100 Ethernet MACs with MII interface |
| | Industry-standard networking interface lowers system bill of materials (BOM) cost | | Multiple ports allow:
| Lower system cost | | Multiple LAN port support | | Concatenation of networking modules |
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UTOPIA-2 Interface with multiple ADSL/G.SHDSL or VDSL PHY support | Industry standard WAN interface |
Two high-speed serial (HSS) ports for connecting to T1/E1 or SLIC/CODECs | Connects to T1/E1 or SLIC/CODECs for voice support |
Silicon functional assistance for Random Number Generation | Accelerates public key exchange and authentication and key generation |
Integrated hardware support for popular cryptography algorithms | Acceleration for popular applications such as IPSec and SSL VPNs (AES/AES-CCM/3DES/DES/SHA-1/SHA-256/ SHA-384/SHA-512/MD-5/RSA/DSA/Diffie-Hellman algorithms) |
Hardware support for IEEE1588 protocol | Hardware assistance for Time Synchronization in a distributed control system containing multiple clocks |
Two high-speed UARTs support up to 921Kbaud each | Provides an interface for debug and passing control information |
Integrated I2C and SSP interfaces | Provides serial interfaces for common embedded and communications application: reduces system BOM cost |
Spread spectrum clocking | Improves system reliability by reducing EMI |
Comprehensive pre-validated pre-integrated "out-of-the-box" development infrastructures ready for application development using Linux*, VxWorks* | Ease of design and fast time-to-market |
544-Ball PBGA Package
| 35mm x 35mm, 1.27mm ball pitch | | Lead-free packages available | | Commercial temperature (0° to 70° C) | | Extended temperature (-40° to 85° C) |
| | High-performance package provides improved reliability | | Lead-free packages help to meet environmental regulations | | Extended temperature support for industrial control and automation applications
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